Channel Plus 8051 Specifikace

Features• 8-bit Microcontroller Compatible with MCS®51 Products• Enhanced 8051 Architecture– Single-clock Cycle per Byte Fetch– Up to 20 MIPS Throughp

103706C–MICRO–2/11AT89LP3240/6440There is no difference in counting rate between Timer 2’s Auto-Reload/Capture and Bau dRate/Clock Out modes. All mode

1003706C–MICRO–2/11AT89LP3240/6440Figure 17-2. SPI Master-Slave InterconnectionWhen the SPI is configured as a Master (MSTR in SPCR is set), the opera

1013706C–MICRO–2/11AT89LP3240/6440and if the ENH bit in SPSR is set. For multi-byte transfers, TXE may be used to remove anydead time between byte tra

1023706C–MICRO–2/11AT89LP3240/6440.Notes:1.In these modes MOSI is active only during transfers. MOSI will be pulled high between trans-fers to allow o

1033706C–MICRO–2/11AT89LP3240/6440Notes:1.Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE.

1043706C–MICRO–2/11AT89LP3240/644017.4 Serial Clock TimingThe CPHA, CPOL and SPR bits in SPCR control the shape and rate of SCK. The two SPR bitsprovi

1053706C–MICRO–2/11AT89LP3240/644018. Two-Wire Serial InterfaceThe Two-Wire Interface (TWI) is a bi-directional 2-wire serial communication standard.

1063706C–MICRO–2/11AT89LP3240/644018.1 Data Transfer and Frame Format18.1.1 Transferring BitsEach data bit transferred on the TWI bus is accompanied b

1073706C–MICRO–2/11AT89LP3240/6440ter’s requ est, the SDA line should be left high in the ACK clock cycle. The Master can thentransmit a STOP conditio

1083706C–MICRO–2/11AT89LP3240/644018.1.5 Combining Address and Data Packets Into a TransmissionA transmission basically consists of a START condition,

1093706C–MICRO–2/11AT89LP3240/6440Figure 18-7. SCL Synchronization between Multiple MastersArbitration is carried out by all masters continuously moni

113706C–MICRO–2/11AT89LP3240/64403. Memory OrganizationThe AT89LP3240/6440 uses a Harvard Architecture with separate address spaces for programand dat

1103706C–MICRO–2/11AT89LP3240/6440It is the user software’s responsibility to ensure tha t these illegal arbitration conditions neveroccur. This impli

1113706C–MICRO–2/11AT89LP3240/6440average TWI bus clock period. The SCL frequency is generated according to the followingequation:18.3.3 Bus Interface

1123706C–MICRO–2/11AT89LP3240/644018.4 Register OverviewTable 18-1. TWCR – Two-Wire Control RegisterTWCR Address = AAH Reset Value = X000 00XXBNot Bit

1133706C–MICRO–2/11AT89LP3240/644018.5 Using the TWIThe AT89LP TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events,li

1143706C–MICRO–2/11AT89LP3240/6440Figure 18-10. Interfacing the Application to the TWI in a Typical Transmission1. The first step in a TWI transmissio

1153706C–MICRO–2/11AT89LP3240/6440long as the TWIF bit in TWCR is set. Immediately after the application has cleared TWIF, the TWI will initiate trans

1163706C–MICRO–2/11AT89LP3240/6440SLA: Slave AddressIn Figure 18-11 to Figure 18-14, circles are used to indicate that the TWIF flag is set. The num-

1173706C–MICRO–2/11AT89LP3240/6440.Table 18-6. Status Codes for Master Transmitter ModeStatus Code(TWSR)Status of the Two-wire Serial Bus and Two-wire

1183706C–MICRO–2/11AT89LP3240/6440Figure 18-11. Format and States in Master Transmitter Mode18.6.2 Master Receiver ModeIn the Master Receiver mode, a

1193706C–MICRO–2/11AT89LP3240/6440TWEN must be written to one to enable the Two-wire Serial Interface, STA must be written toone to transmit a START c

123706C–MICRO–2/11AT89LP3240/6440Figure 3-1. Program Memory Map3.2 Internal Data MemoryThe AT89LP3240/6440 contains 256 bytes of general SRAM data mem

1203706C–MICRO–2/11AT89LP3240/6440Figure 18-12. Format and States in Master Receiver Mode18.6.3 Slave Receiver ModeIn the Slave Receiver mode, a numbe

1213706C–MICRO–2/11AT89LP3240/6440TWEN must be written to one to enable the TWI. The AA bit must be written to one to enable theacknowledgment of the

1223706C–MICRO–2/11AT89LP3240/6440Figure 18-13. Format and States in Slave Receiver Mode88hPreviously addressed with own SLA+W; data has been received

1233706C–MICRO–2/11AT89LP3240/644018.6.4 Slave Transmitter ModeIn the Slave Transmitter mode, a number of data bytes are transmitted to a master recei

1243706C–MICRO–2/11AT89LP3240/6440.Table 18-9. Status Codes for Slave Transmitter ModeStatus Code(TWSR)Status of the Two-wire Serial Bus and Two-wire

1253706C–MICRO–2/11AT89LP3240/644018.6.5 Miscellaneous StatesThere are two status codes that do not correspond to a defined TWI state, see Table 18-10

1263706C–MICRO–2/11AT89LP3240/6440Figure 18-15. Combining Several TWI Modes to Access a S erial EEPROM19. Dual Analog ComparatorsThe AT89LP3240/6440

1273706C–MICRO–2/11AT89LP3240/6440als o set the CONA (ACSRA.5) or CONB (ACSRB.5) bits to connect the compara tor inputsbefore using a comparator. When

1283706C–MICRO–2/11AT89LP3240/6440Figure 19-2. Equivalent Analog Input Model19.2 Internal Reference VoltageThe negative input terminal of each compara

1293706C–MICRO–2/11AT89LP3240/6440Figure 19-4. Dual Comparator Configuration Examplesa. dual independent comparators with external references+-ACMPAAI

133706C–MICRO–2/11AT89LP3240/64403.2.2 IDATAThe full 256 byte internal RAM can be indirectly addressed using the 8-bit pointers R0 and R1.The first 12

1303706C–MICRO–2/11AT89LP3240/6440Notes:1.CONA must be cleared to 0 before changing CSA[1-0].2. Debouncing modes require the use of Timer 1 to generat

1313706C–MICRO–2/11AT89LP3240/6440Notes:1.CONB must be cleared to 0 before changing CSB[1-0].2. Debouncing modes require the use of Timer 1 to generat

1323706C–MICRO–2/11AT89LP3240/6440Notes:1.CONB (ACSRB.5) must be cleared to 0 before changing RFB[1-0].2. CONA (ACSRA.5) must be cleared to 0 before c

1333706C–MICRO–2/11AT89LP3240/644020. Digital-to-Analog/Analog-to-Digital ConverterThe AT89LP3240/6440 includes a 10-bit Data Converter (DADC) with th

1343706C–MICRO–2/11AT89LP3240/6440Figure 20-1. DADC Block DiagramTable 20-1. Example ADC Conversion CodesRight Adjust Left Adjust Single-Ended Mode (V

1353706C–MICRO–2/11AT89LP3240/644020.1 ADC OperationThe ADC converts an analog input voltage to a 10-bit signed digital value through successiveapprox

1363706C–MICRO–2/11AT89LP3240/6440Figure 20-3. Equivalent Analog Input Model20.2 DAC OperationThe DAC converts a 10-bit signed digital value to an ana

1373706C–MICRO–2/11AT89LP3240/6440Figure 20-5. Equivalent Analog Output Model20.3 Clock SelectionThe DADC requires a clock of 2 MHz or less to achieve

1383706C–MICRO–2/11AT89LP3240/6440be set by hardware while the conversion is in progress. Note that the timer overflow rate must beslower than the con

1393706C–MICRO–2/11AT89LP3240/6440Table 20-2. DADC – DADC Control RegisterDADC = D9H Reset Value = 0000 0000BNot Bit AddressableADIF GO/BSYDAC ADCE LA

143706C–MICRO–2/11AT89LP3240/6440Some internal data memory s paces are mapped into portions of the XDATA address space. Inthis case the lower address

1403706C–MICRO–2/11AT89LP3240/6440Table 20-5. DADI – DADC Input Control RegisterDADI = DAH Reset Value = 0000 0000BNot Bit AddressableACON IREFTRG1 TR

1413706C–MICRO–2/11AT89LP3240/644021. Programmable Watchdog TimerThe programmable Watchdog Timer (WDT) protects the system from incorrect execution by

1423706C–MICRO–2/11AT89LP3240/644021.1 Software ResetA Software Reset of the AT89LP3240/6440 is accomplished by writing the software resetsequence 5AH

1433706C–MICRO–2/11AT89LP3240/644022. Instruction Set SummaryThe AT89LP3240/6440 is fully binary compatible with the 8051 instruction set. The differe

1443706C–MICRO–2/11AT89LP3240/6440INC /DPTR(1)2– 3A5 A3MUL AB 1 48 2A4DIV AB 1 48 4 84DA A 1 12 1 D4MAC AB(1)2– 9A5 A4CLR M(1)2– 2A5 E4ASR M(1)2– 2A5

1453706C–MICRO–2/11AT89LP3240/6440XRL A, direct 2 12 2 65XRL A, @Ri 1 12 2 66-67XRL A, #data 212 2 64XRL direct, A 2 12 2 62XRL direct, #data 324 3 63

1463706C–MICRO–2/11AT89LP3240/6440Notes:1.This escaped instruction is an extension to the instruction set. See Section 22.1 on page 147.2. MOVX @DPTR

1473706C–MICRO–2/11AT89LP3240/644022.1 Instruction Set ExtensionsThe following instructions are extensions to the standard 8051 instruction set that p

1483706C–MICRO–2/11AT89LP3240/644022.1.3 CJNE A, @Ri, relFunction: Compare and Jump if Not EqualDescription: CJNE compares the magnitudes of the Accum

1493706C–MICRO–2/11AT89LP3240/644022.1.5 INC /DPTRFunction: Increment Alternate Data PointerDescription: INC /DPTR increments the unselected 16-bit da

153706C–MICRO–2/11AT89LP3240/6440To enable write access to the nonvolatile data memory, the MWEN bit (MEMCON.4) must be setto one. When MWEN = 1 and D

1503706C–MICRO–2/11AT89LP3240/644022.1.7 LSL MFunction: Shift MAC Accumulator Left LogicallyDescription: The forty bits in the M register are shifted

1513706C–MICRO–2/11AT89LP3240/644022.1.9 MAC ABFunction: Multiply and AccumulateDescription: MAC AB multiplies the signed 16-bit integers in the regis

1523706C–MICRO–2/11AT89LP3240/644022.1.11 MOVX A, @/DPTRFunction: Move External using Alternate Data PointerDescription: The MOVX instruction transfes

1533706C–MICRO–2/11AT89LP3240/644023. Register IndexTable 23-1. Special Function Register Cross ReferenceName Address Description IndexACC E0HACSRA 97

1543706C–MICRO–2/11AT89LP3240/6440P1 90H Table 10-3 on page 45P1M0 C2H Table 10-2 and Table 10-3 on page 45P1M1 C3H Table 10-2 and Table 10-3 on page

1553706C–MICRO–2/11AT89LP3240/644024. On-Chip Debug SystemThe AT89LP3240/6440 On-Chip Debug (OCD) System uses a two-wire serial interface to con-trol

1563706C–MICRO–2/11AT89LP3240/6440• P4.2/RST ca nnot be connected directly to VDD and any external capacitors connected to RST must be removed.• All e

1573706C–MICRO–2/11AT89LP3240/6440• When using the Internal RC Oscillator during debug, DDA is located on the XTAL1/P4.0 pin. The P4.0 I/O function ca

1583706C–MICRO–2/11AT89LP3240/6440Figure 25-1. In-System Programming Device ConnectionsThe Parallel interface is a special mode of the serial interfac

1593706C–MICRO–2/11AT89LP3240/6440•The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a maximum frequency of 5 MHz.•The

163706C–MICRO–2/11AT89LP3240/6440Figure 3-5. FDATA Byte WriteFigure 3-6. FDATA Page WriteFrequently just a few bytes within a page must be updated whi

1603706C–MICRO–2/11AT89LP3240/6440Figure 25-3. AT89LP6440 Memory Organization25.3 Command FormatProgramming commands consist of an opcode byte, two ad

1613706C–MICRO–2/11AT89LP3240/6440For a summary of available commands, see Table 25-2 on page 162.Figure 25-4. Command Sequence Flow ChartFigure 25-5.

1623706C–MICRO–2/11AT89LP3240/6440Notes:1.Program Enable must be the first command issued after entering into programming mode.2. Parallel Enable swit

1633706C–MICRO–2/11AT89LP3240/644025.4 Status RegisterThe current state of the memory may be accessed by reading the status register. The status reg-i

1643706C–MICRO–2/11AT89LP3240/644025.7 User Configuration FusesThe AT89LP3240/6440 includes 11 user fuses for configuration of the device. Each fuse i

1653706C–MICRO–2/11AT89LP3240/644025.8 User Signature and Analog ConfigurationThe User Signature Array contains 256 bytes of non-volatile memory in tw

1663706C–MICRO–2/11AT89LP3240/6440Figure 25-7. Serial Programming Power-up Sequence25.9.2 Power-down Sequence Execute this sequence to power-down the

1673706C–MICRO–2/11AT89LP3240/6440Figure 25-9. In-System Programming (ISP) Start Sequence25.9.4 ISP Exit Sequence Execute this sequence to exit ISP mo

1683706C–MICRO–2/11AT89LP3240/6440CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge ofSCK. For more detailed t

1693706C–MICRO–2/11AT89LP3240/644025.9.6 Timing ParametersThe timing parameters for Figure 25-7, Figure 25-8, Figure 25-9, Figure 25-10, Figure 25-12

173706C–MICRO–2/11AT89LP3240/64403.3.4 External Memory InterfaceThe AT89LP3240/6440 uses the standard 8051 external memory interface with the upperadd

1703706C–MICRO–2/11AT89LP3240/644026. Electrical CharacteristicsNotes: 1. Under steady state (non-transient) conditions, IOL must be externally limite

1713706C–MICRO–2/11AT89LP3240/644026.3 Safe Operating Conditions26.3.1 SpeedFigure 26-1 shows the safe operating frequencies for the AT89LP3240/6440 v

1723706C–MICRO–2/11AT89LP3240/644026.4.1 Supply Current (Internal Oscillator)Figure 26-3. Active Supply Current vs. VDD (8MHz Internal Oscillator)Figu

1733706C–MICRO–2/11AT89LP3240/644026.4.2 Supply Current (External Clock)Figure 26-5. Active Supply Current vs. FrequencyFigure 26-6. Idle Supply Curre

1743706C–MICRO–2/11AT89LP3240/644026.4.3 Quasi-Bidirectional InputFigure 26-7. Quasi-bidirectional Input Transition Current at 3.3V26.4.4 Quasi-Bidire

1753706C–MICRO–2/11AT89LP3240/644026.4.5 Push-Pull OutputFigure 26-9. Push-Pull Output I-V Source Characteristic at 3VFigure 26-10. Push-Pull Output I

1763706C–MICRO–2/11AT89LP3240/6440The values shown in these tables are valid for TA = -40°C to 85°C and VDD = 2.4 to 3.6V, unless otherwise noted.Note

1773706C–MICRO–2/11AT89LP3240/6440Figure 26-13. Typical Crystal Oscillator Swing with Quartz Crystal and C1=C2, TA = 25°CNote: 1. Replacing capacitor

1783706C–MICRO–2/11AT89LP3240/644026.6 Reset CharacteristicsThe values shown in this table are valid for TA = -40°C to 85°C and VDD = 2.4 to 3.6V, unl

1793706C–MICRO–2/11AT89LP3240/64403. Parameter tLHLL applies only when ALES =1.4. The strobe pulse width may be lengthened by 1, 2 or 3 additional tCL

183706C–MICRO–2/11AT89LP3240/6440Figure 3-8 shows a hardware configuration for accessing 256-byte blocks of external RAM usingan 8-bit paged address.

1803706C–MICRO–2/11AT89LP3240/6440Figure 26-17. SPI Master Timing (CPHA = 0)tSISSerial Input Setup Time 10 nstSIHSerial Input Hold Time 10 nstSOHSeria

1813706C–MICRO–2/11AT89LP3240/6440Figure 26-18. SPI Slave Timing (CPHA = 0)Figure 26-19. SPI Master Timing (CPHA = 1)Figure 26-20. SPI Slave Timing (C

1823706C–MICRO–2/11AT89LP3240/644026.9 Two-wire Serial Interface CharacteristicsTable 26-7 describes the requirements for devices connected to the Two

1833706C–MICRO–2/11AT89LP3240/64403. Cb = capacitance of one bus line in pF.4. fCK = CPU clock frequencyFigure 26-21. Two-wire Serial Bus Timing Figur

1843706C–MICRO–2/11AT89LP3240/644026.11 Dual Analog Comparator CharacteristicsThe values shown in this table are valid for TA = -40°C to 85°C and VDD

1853706C–MICRO–2/11AT89LP3240/644026.12 DADC CharacteristicsThe values shown in these tables are valid for TA = -40°C to 85°C and VDD = 2.4 to 3.6V, u

1863706C–MICRO–2/11AT89LP3240/644026.13 Test Conditions26.13.1 AC Testing Input/Output WaveformFigure 26-24. AC Testing Input/Output Waveform(1) Note:

1873706C–MICRO–2/11AT89LP3240/644026.13.4 ICC Test Condition: Idle ModeFigure 26-27. Connection Diagram for ICC Idle Measurement. All Other Pins are D

1883706C–MICRO–2/11AT89LP3240/644027. Ordering Information 27.1 Green Package Option (Pb/Halide-free)Code FlashSpeed (MHz)PowerSupply Ordering Code Pa

1893706C–MICRO–2/11AT89LP3240/644028. Packaging Information28.1 44A – TQFP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 44A, 44-le

193706C–MICRO–2/11AT89LP3240/6440automatically tristated when inputting data regardless of the Port 0 configuration. The Port 0configuration will dete

1903706C–MICRO–2/11AT89LP3240/644028.2 40P6 – PDIP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 40P6, 40-lead (0.600"/15.24 m

1913706C–MICRO–2/11AT89LP3240/644028.3 44J – PLCCNotes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do n

1923706C–MICRO–2/11AT89LP3240/644028.4 44M1 – VQFN/MLFTITLEDRAWING NO.GPCREV. Package Drawing Contact: [email protected] H44M1, 44-p

1933706C–MICRO–2/11AT89LP3240/644029. Revision History Revision No. HistoryRevision A – September 2009 • Initial ReleaseRevision B– September 2010• Re

1943706C–MICRO–2/11AT89LP3240/6440

i3706C–MICRO–2/11AT89LP3240/6440Table of ContentsFeatures ...

ii3706C–MICRO–2/11AT89LP3240/6440Table of Contents (Continued)7.4 Watchdog Reset ...

iii3706C–MICRO–2/11AT89LP3240/6440Table of Contents (Continued)16 Serial Interface (UART) ...

iv3706C–MICRO–2/11AT89LP3240/6440Table of Contents (Continued)22 Instruction Set Summary ...

v3706C–MICRO–2/11AT89LP3240/6440Table of Contents (Continued)28 Packaging Information ...

23706C–MICRO–2/11AT89LP3240/64401. Pin Configurations1.1 40P6: 40-lead PDIP1.2 44A: 44-lead TQFP (Top View)1234567891011121314151617181920403938373635

203706C–MICRO–2/11AT89LP3240/6440Figure 3-11. MOVX with One Wait State (WS =01B)Figure 3-12. MOVX with Two Wait States (WS =10B)Figure 3-13. MOVX with

3706C–MICRO–2/11Atmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: (+1) (408) 441-0311Fax: (+1) (408) [email protected]

213706C–MICRO–2/11AT89LP3240/6440tain separate copies of SP for use with each stack space. Interrupts should be disabled whileswapping copies of SP in

223706C–MICRO–2/11AT89LP3240/64404. Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space is sho

233706C–MICRO–2/11AT89LP3240/64405. Enhanced CPUThe AT89LP3240/6440 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed ofstandard 8051 dev

243706C–MICRO–2/11AT89LP3240/6440Figure 5-3. Two-cycle ALU Operation (Example: ADD A, #data)5.1 Multiply–Accumulate Unit (MAC)The AT89LP3240/6440 incl

253706C–MICRO–2/11AT89LP3240/6440The MAC operation is performed by executing the MAC AB (A5 A4H) extended instruction. Thistwo-byte instruction requir

263706C–MICRO–2/11AT89LP3240/6440•In some cases, both data pointers must be used simultaneously. To prevent frequent toggling of DPS, the AT89LP3240/6

273706C–MICRO–2/11AT89LP3240/6440A summary of data pointer instructions with fast context switching is listed inTable 5-2.5.2.1 Data Pointer UpdateThe

283706C–MICRO–2/11AT89LP3240/64405.2.2 Data Pointer Operating ModesThe Dual Data Pointers on the AT89LP3240/6440 include three additional operating mo

293706C–MICRO–2/11AT89LP3240/64405.2.2.2 Index DisableThe MOVC Index Disable bit, MVCD (DSPR.1), disables the indexed addressing mode of theMOVC A, @A

33706C–MICRO–2/11AT89LP3240/64401.3 44J: 44-lead PLCC1.4 44M1: 44-pad VQFN/MLF7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 MOSI/P1.5

303706C–MICRO–2/11AT89LP3240/64405.3 Instruction Set ExtensionsTable 5-8 lists the additions to the 8051 instruction set that are supported by theAT89

313706C–MICRO–2/11AT89LP3240/64406. System ClockThe system clock is generated directly from one of three selectable clock sources. The threesources ar

323706C–MICRO–2/11AT89LP3240/64406.2 External Clock SourceThe external clock option disables the oscillator amplifier and allows XTAL1 to be driven di

333706C–MICRO–2/11AT89LP3240/6440pass through intermediate frequencies. When CDV is updated, the new frequency will takeaffect within a maximum period

343706C–MICRO–2/11AT89LP3240/6440generated reset can be extended beyond the power-on period by holding the RST pin low longerthan the time-out.Figure

353706C–MICRO–2/11AT89LP3240/6440meet the minimum system requirements before the device exits reset and starts normal opera-tion. The RST pin may be h

363706C–MICRO–2/11AT89LP3240/6440Note: During a power-up sequence, the fuse selection is always overridden and therefore the pin will always function

373706C–MICRO–2/11AT89LP3240/6440.8.2 Power-down ModeSetting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stopsthe oscillat

383706C–MICRO–2/11AT89LP3240/6440Figure 8-1. Interrupt Recovery from Power-down (PWDEX = 0)When PWDEX = “1”, the wake-up period is controlled external

393706C–MICRO–2/11AT89LP3240/6440Figure 8-3. Reset Recovery from Power-down8.3.2 Analog ComparatorsThe comparators will operate during Idle mode if e

43706C–MICRO–2/11AT89LP3240/64401.5 Pin DescriptionTable 1-1. AT89LP3240/6440 Pin DescriptionPin NumberSymbol Type DescriptionTQFP PLCC PDIP VQFN1761P

403706C–MICRO–2/11AT89LP3240/6440The IPxD bits located at the seventh bit of IP, IPH, IP2 and IP2H can be used to disable all inter-rupts of a given p

413706C–MICRO–2/11AT89LP3240/64409.1 Interrupt Response TimeThe interrupt flags may be set by their hardware in any clock cycle. The interrupt control

423706C–MICRO–2/11AT89LP3240/6440rupt system, the response time is always more than 5 clock cycles and less than 21 clock cycles.See Figure 9-1 a nd F

433706C–MICRO–2/11AT89LP3240/6440Table 9-3. IE2 – Interrupt Enable 2 RegisterIE = B4H Reset Value = xxxx x000BNot Bit Addressable– – – ETWI EADC ESPI

443706C–MICRO–2/11AT89LP3240/6440PSP Serial Peripheral Interface Interrupt Priority LowPCC Compare/Capture Array Interrupt Priority LowPGP General-pur

453706C–MICRO–2/11AT89LP3240/644010. I/O PortsThe AT89LP3240/6440 can be configured for between 35 and 38 I/O pins. The exact number ofI/O pins availa

463706C–MICRO–2/11AT89LP3240/644010.1.1 Quasi-bidirectional OutputPort pins in quasi-bidirectional output mode function similar to standard 8051 port

473706C–MICRO–2/11AT89LP3240/6440Figure 10-3. Input Circuit for P3.2, P3.3, P4.0, P4.1 and P4.210.1.3 Open-drain OutputThe open-drain output configura

483706C–MICRO–2/11AT89LP3240/644010.2 Port Analog FunctionsThe AT89LP3240/6440 incorporates two analog comparators and an 8-channel analog-to-digitalc

493706C–MICRO–2/11AT89LP3240/644010.4 Port Alternate FunctionsMost general-purpose digital I/O pins of the AT89LP3240/6440 share functionality with th

53706C–MICRO–2/11AT89LP3240/644017 23 20 17 GND I Ground18 24 21 18 P2.0I/OI/OOP2.0: User-configurable I/O Port 2 bit 0.CCA: Timer 2 Channel A Compare

503706C–MICRO–2/11AT89LP3240/6440P1.2 P1M0.2 P1M1.2SDA open-drainGPI2P1.3 P1M0.3 P1M1.3SCL open-drainGPI3P1.4 P1M0.4 P1M1.4SSGPI4P1.5 P1M0.5 P1M1.5MOS

513706C–MICRO–2/11AT89LP3240/644011. Enhanced Timer 0 and Timer 1 with PWMThe AT89LP3240/6440 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with

523706C–MICRO–2/11AT89LP3240/644011.1 Mode 0 – Variable Width Timer/CounterBoth Timers in Mode 0 are 8-bit Counters with a variable prescaler. The pre

533706C–MICRO–2/11AT89LP3240/6440Figure 11-2. Timer/Counter 1 Mode 1: 16-bit Auto-Reload11.3 Mode 2 – 8-bit Auto-Reload Timer/CounterMode 2 configures

543706C–MICRO–2/11AT89LP3240/6440Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, theAT89LP3240/6440 can

553706C–MICRO–2/11AT89LP3240/6440Table 11-3. TMOD – Timer/Counter Mode Control RegisterTMOD Address = 089H Reset Value = 0000 0000BNot Bit Addressable

563706C–MICRO–2/11AT89LP3240/644011.5 Pulse Width ModulationOn the AT8 9LP3240/6440, Timer 0 and Timer 1 may be independently configured as 8-bitasymm

573706C–MICRO–2/11AT89LP3240/644011.5.1 Mode 0 – 8-bit PWM with 8-bit Logarithmic PrescalerIn Mode 0, TLx acts as a logarithmic prescaler driving 8-bi

583706C–MICRO–2/11AT89LP3240/6440Figure 11-7. Timer/Counter 1 PWM Mode 1Figure 11-8. Timer/Counter 1 PWM Mode 2Note: {RH0 & RL0}/{RH1 & RL1} a

593706C–MICRO–2/11AT89LP3240/644011.5.4 Mode 3 – Split 8-bit PWMTimer 1 in PWM Mode 3 simply holds its count. The effect is the same as setting TR1 =

63706C–MICRO–2/11AT89LP3240/64402. OverviewThe AT89LP3240/6440 is a low-power, high-performance CMOS 8-bit microcontroller with32K/64K b ytes of In-Sy

603706C–MICRO–2/11AT89LP3240/644012. Enhanced Timer 2The AT89LP3240/6440 includes a 16-bit Timer/Counter 2 with the following features:•16-bit timer/c

613706C–MICRO–2/11AT89LP3240/644012.1 Timer 2 RegistersControl and status bits for Timer 2 are contained in registers T2CON (see Table 12-3) andT2MOD

623706C–MICRO–2/11AT89LP3240/644012.2 Capture ModeIn the Capture mode, Timer 2 is a fixed 16-bit timer or counter that counts up from MIN to MAX.An ov

633706C–MICRO–2/11AT89LP3240/6440Figure 12-1. Timer 2 Diagram: Capture Mode 12.3 Auto-Reload ModeTimer 2 can be programmed to count up or down when co

643706C–MICRO–2/11AT89LP3240/6440RCAP2L and then overflows. The overflow sets TF2 and causes the timer registers to bereloaded with MIN. If EXEN2 = 1,

653706C–MICRO–2/11AT89LP3240/6440registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timerunderflows when TH2 and TL

663706C–MICRO–2/11AT89LP3240/6440Figure 12-6. Timer 2 Waveform: Auto-Reload Mode (DCEN = 1)12.3.3 Dual Slope CounterWhen Timer 2 Auto-Reload Mode uses

673706C–MICRO–2/11AT89LP3240/6440Figure 12-7. Timer 2 Waveform: Dual Slope Modes12.4 Baud Rate GeneratorTimer 2 is selected as the baud rate generator

683706C–MICRO–2/11AT89LP3240/6440erator, T2EX can be used as an extra external interrupt. Also note that the Baud Rate andFrequency Generator modes ma

693706C–MICRO–2/11AT89LP3240/6440Figure 12-9. Timer 2 in Clock-out Mode13. Compare/Capture ArrayThe AT89LP3240/6440 includes a four channel Compa re/C

73706C–MICRO–2/11AT89LP3240/6440Timer 0 and Timer 1 in the AT89LP3240/6440 are enhanced with two new modes. Mode 0 canbe configured as a variable 9- t

703706C–MICRO–2/11AT89LP3240/6440Figure 13-1. Compare/Capture Array Block Diagram13.1 CCA RegistersThe Compare/Capture Array has five Special Function

713706C–MICRO–2/11AT89LP3240/6440Note: All writes/reads to/from T2CCH will access channel X as currently selected by T2CCA.The data registers for the

723706C–MICRO–2/11AT89LP3240/644013.2 Input Capture ModeThe Compare/Capture Array provides a variety of capture modes suitable for time-stampingevents

733706C–MICRO–2/11AT89LP3240/6440to occur at a negative edge, positive edge, or both (toggle). Capture inputs are sampled everyclock cycle and a new v

743706C–MICRO–2/11AT89LP3240/6440Notes: 1. All writes/reads to/from T2CCC will access channel X as currently selected by T2CCA.The control registers f

753706C–MICRO–2/11AT89LP3240/644013.3 Output Compare ModeThe Compare/Capture Array provides a variety of compare modes suitable for event timing orwav

763706C–MICRO–2/11AT89LP3240/644013.3.1.1 Normal ModeThe simplest waveform mode is when CP/RL2=0 and T2CM1-0 = 01B. In this mode the fre-quency of the

773706C–MICRO–2/11AT89LP3240/6440Figure 13-6. Dual-Slope Waveform Example13.3.2 Timer 2 Operation for Compare ModeCompare channels will work with any

783706C–MICRO–2/11AT89LP3240/644013.4.1 Asymmetrical PWMFor Asymmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 1(CP/RL

793706C–MICRO–2/11AT89LP3240/6440center-aligned around the timer equal to TOP point. Symmetrical PWM may be used to generatenon-overlapping waveforms.

83706C–MICRO–2/11AT89LP3240/64402.2 System ConfigurationThe AT89LP3240/6440 supports several system configuration options. Nonvolatile options areset

803706C–MICRO–2/11AT89LP3240/6440Figure 13-10. Phase and Frequency Correct Symmetrical (Center-Aligned) PWMFigure 13-11. Phase Correct Symmetrical (Ce

813706C–MICRO–2/11AT89LP3240/6440Figure 13-12. Multi-Phasic PWM Outpu t StageFigure 13-13. Three-Phase Mode with Channel B DisabledTable 13-6. Summary

823706C–MICRO–2/11AT89LP3240/6440Figure 13-14. Multi-Phasic PWM Modes14. External InterruptsThe INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP3240/644

833706C–MICRO–2/11AT89LP3240/6440another interrupt will be generated. Both INT0 and INT1 may wake up the device from thePower-down state.15. General-p

843706C–MICRO–2/11AT89LP3240/6440...Table 15-1. GPMOD – General-purpose Interrupt Mode RegisterGPMOD = 9AH Reset Value = 0000 0000BNot Bit Addressable

853706C–MICRO–2/11AT89LP3240/644016. Serial Interface (UART)The serial interface on the AT89LP3240/6440 implements a Universal AsynchronousReceiver/Tr

863706C–MICRO–2/11AT89LP3240/6440bit and prepares to receive the data bytes that follows. The slaves that are not addressed settheir SM2 bits and ign

873706C–MICRO–2/11AT89LP3240/644016.2 Baud RatesThe baud rate in Mode 0 depends on the value of the SMOD1 bit in Specia l Function RegisterPCON.7. If

883706C–MICRO–2/11AT89LP3240/644016.2.2 Using Timer 2 to Generate Baud RatesTimer 2 is selected as the baud rate generator by setting TCLK and/or RCLK

893706C–MICRO–2/11AT89LP3240/644016.3 More About Mode 0In Mode 0, the UART is configured as a two wire half-duplex synchronous serial interface. Seria

93706C–MICRO–2/11AT89LP3240/64402.3 Comparison to Standard 8051The AT89LP3240/6440 is part of a family of devices with enhanced features that are full

903706C–MICRO–2/11AT89LP3240/6440Figure 16-1. Serial Port Mode 0INTERNAL BUSfoscINTERNAL BUSTXD (SHIFT CLOCK)RXD (DATA OUT)TXD (SHIFT CLOCK)RXD (DATA

913706C–MICRO–2/11AT89LP3240/6440Figure 16-2. Mode 0 WaveformsMode 0 may be used as a hardware accelerator for software emulation of serial interfaces

923706C–MICRO–2/11AT89LP3240/644016.4 More About Mode 1Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits

933706C–MICRO–2/11AT89LP3240/6440Figure 16-4. Serial Port Mode 1 TXCLOCKWRITE TO SBUFINTERNAL BUSREADSBUFLOADSBUFSBUFSHIFTINPUT SHIFT REG.(9 BITS)BITD

943706C–MICRO–2/11AT89LP3240/644016.5 More About Modes 2 and 3Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8

953706C–MICRO–2/11AT89LP3240/6440Figure 16-5. Serial Port Mode 2SMOD1 1SMOD1 0INTERNAL BUSINTERNAL BUSCPU CLOCK

963706C–MICRO–2/11AT89LP3240/6440Figure 16-6. Serial Port Mode 3 TXCLOCKWRITE TO SBUFSENDDATASHIFTTXDSTOP BIT GENTID0 D1 D2 D3 D4 D5 D6 D7 TB8STOP BIT

973706C–MICRO–2/11AT89LP3240/644016.6 Framing Error DetectionIn addition to all of its usual modes, the UART can perform framing error detection by lo

983706C–MICRO–2/11AT89LP3240/6440In a more complex system, the following could be used to select slaves 1 and 2 while excludingslave 0: Slave 0 SADDR

993706C–MICRO–2/11AT89LP3240/6440Figure 17-1. SPI Block DiagramThe interconnection between master and slave CPUs with SPI is shown in Figure 17-2. The